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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

what is the most effecient memory design

A topic by goADX created May 30, 2025 Views: 904 Replies: 10
Viewing posts 1 to 6

i am getting 70 steps per second my whole project is slow i only have 256 bytes of memory with a couple of 1 bytes here and there so what is the most effecient way to make memory/ram

(i think the simulation could have some multithreading but idk)

The better way is to use a RGD display. It has 8 bits address and 12 bits I/O data color. So, you can use the 8 bits address and 2 colors ( a nibble each) to get 8 bits I/O data line.

Or you can use the extra color channel for the instruction, so you can free bits for your data.

the good thing about this ram is that it starts empty, unlike normal d-latch-grid or grid of registers.

But if you want to make it real, RGB display is nonsense.  You can make a RAM with so many and gates and not gates. For 2^n bytes. There will be n registers, n not gates and 2n ands. If you make and gates with tri-state buffers, it will be faster. But this will be maybe more complex than version with decoders. I recommend Sebastian's RAM in his latest video.

(-1)

I did a 65536 Bytes Ram.

What did you use? How is it possible to run the simulation unless you don't use logic gates as the main...?

RBG. like they said. same structure as Sebastians ram video just with an address

I am copying you

(1 edit)

HOW THE HELL MY COMPUTER IS HANDLNG A 65536X16 RAM AT 60 STEPS/S

I found another way to make 8 bit memory unit. It can be stacked to get more RAM and it can be faster than regular gate based memory (depends on how optimized your memory units are).


Here's a picture of the memory:It stores the byte by feeding the current value back into the 3-state buffer. The bus acts like a small buffer and a way to merge the outputs of the two 3-state buffers. Writing to the memory will first put the value into the bottom 3-state buffer and when the clock signal goes low, then the active 3-state buffer will switch. The bus needs a tick to clear, so switching the active 3-state buffer will preserve the data in the bus, until the upper 3-state buffer takes over.

For a reference on how fast this chip is: I modded the game myself to get an incredibly fast D-Latch chip, which I wired 8 together to make a byte. This version is 40% faster than the one with the built-in chips. For me it executes at a speed of ~2'500'000 tick per second and the regular one from the gates executes about 800'000 times each second. That is 3.125x faster.
It's not as fast as using displays, but if you feel like displays are cheating, then this is a little less cheating. Although, for 1 byte registers, latches, etc., this is really good.

But if you want to get even more speed, like the whole CPU running at 100'00+ ticks per second, then you have to either find a mod, or mod the game yourself. The source code is in GitHub and you could use AI for help with coding.