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Digital Logic Sim

​A minimalistic digital logic simulator · By Sebastian Lague

NEW CUSTOM 8-BIT CPU

A topic by Bendy509 created Apr 16, 2026 Views: 656 Replies: 13
Viewing posts 1 to 10

(2 edits) (+1)

IT IS 0-3 STEPS. IT IS FETCHED AT STEP 0.

I STILL NEED TO MAKE IMPROVEMENT

---------------------------------- ALU_OP ENCODING -----------------------------

ALU_OP2..ALU_OP0 (Micro B bits 12,11,10):

   000 : ADD

   001 : SUB

   010 : AND

   011 : OR

   100 : XOR

   101 : NOT 

   110 : INC

   111 : DEC 

https://drive.google.com/file/d/1D-SDzgKlAKT5j60bjaFbWhTuVP_6sAxP/view?usp=drive...

Cool! But I have some ideas for improvement:

- External RAM access

-DDR (Double Data Rate) support

I'M NOT REALLY A COMPUTER GUY. I DO IT AS A GAME. 

I CAN SHARE THE FILE AND YOU GUYS CAN MODIFY AND IMPROVE IT: https://drive.google.com/file/d/19L_iY2GA7wIV7NgT5DtGXlwdsDtPnQdO/view?usp=shari...
IT'S A MODIFY VERSION OF PONG! (8-bit computer) - Digital Logic Sim community - itch.io.

why did you delete the file? 

(1 edit)

Try again.


I also have a most upgrade version.

https://drive.google.com/file/d/1DGbkkc-QnZH5b6jvRVbs2T47MCJpNyjB/view?usp=drive...

https://github.com/firecerne/Digital-Logic-Sim-Community-Edit/releases/tag/v1.2.1

https://drive.google.com/file/d/1DB3wN-ObG8QnLCoJ9y1Fcv6yn_NKw_HM/view?usp=drivesdk

It takes time for the ALU to be cached. And you may need to open the CPU chip several due to overclocking or increase the steps per clock tick.

Connect 4 in 7*7 grid

(1 edit)

IT HAS R0-R7 GENERAL PURPOSE REG AND 5 GRAPHICS REG (X, Y, R, G AND B).
IT CAN HAVE UP TO  128 INST SET.
YOU MUST USE THIS DLS 2 VERSION: Release DLS Community Edit v1.2.1 · firecerne/Digital-Logic-Sim-Community-Edit.

---------------------------------- ALU_OP ENCODING -----------------------------

   0000 : ADD       0001 : SUB       0010 : AND       0011 : OR

   0100 : XOR       0101 : NOT       0110 : INC       0111 : DEC

   1000 : MUL       1001 : DIV       1010 : MOD       1011 : SHL

   1100 : SHR       1101 : ROL       1110 : ROR       1111 : NEG

SHL/SHR/ROL/ROR: 0-7

================================================================================

https://drive.google.com/file/d/1v9hGBByIgiNYAESgUkeYV1ik5it8DZAd/view?usp=shari...

I managed to fit breakout into my CPU design 8bit address/data.